Accurate modelling of the queueing behaviour of shared buffer ATM switches

A model for the analysis of multistage switches based on shared bu!er switching for Asynchronous Transfer Mode (ATM) networks is developed, and the results are compared with the simulation. Switches constructed from shared bu!er switches do not su!er from the head of line blocking which is the common problem in simple input bu!ering. The analysis models the state of the entire switch and extends the model introduced by Turner to global #ow control with backpressure mechanism. It is shown that bu!er utilization is better and throughput improves signi"cantly compared with the same switch using local #ow control policy. Copyright ( 1999 John Wiley & Sons, Ltd.